FSWIDTH=SLOT, MCKSEL=GCLK, SCKSEL=MCKDIV, BITDELAY=LJ, FSSEL=SCKDIV, SLOTSIZE=8
Clock Unit n Control
| SLOTSIZE | Slot Size 0 (8): 8-bit Slot for Clock Unit n 1 (16): 16-bit Slot for Clock Unit n 2 (24): 24-bit Slot for Clock Unit n 3 (32): 32-bit Slot for Clock Unit n |
| NBSLOTS | Number of Slots in Frame |
| FSWIDTH | Frame Sync Width 0 (SLOT): Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 1 (HALF): Frame Sync Pulse is half a Frame wide 2 (BIT): Frame Sync Pulse is 1 Bit wide 3 (BURST): Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested |
| BITDELAY | Data Delay from Frame Sync 0 (LJ): Left Justified (0 Bit Delay) 1 (I2S): I2S (1 Bit Delay) |
| FSSEL | Frame Sync Select 0 (SCKDIV): Divided Serial Clock n is used as Frame Sync n source 1 (FSPIN): FSn input pin is used as Frame Sync n source |
| FSINV | Frame Sync Invert |
| FSOUTINV | Frame Sync Output Invert |
| SCKSEL | Serial Clock Select 0 (MCKDIV): Divided Master Clock n is used as Serial Clock n source 1 (SCKPIN): SCKn input pin is used as Serial Clock n source |
| SCKOUTINV | Serial Clock Output Invert |
| MCKSEL | Master Clock Select 0 (GCLK): GCLK_I2S_n is used as Master Clock n source 1 (MCKPIN): MCKn input pin is used as Master Clock n source |
| MCKEN | Master Clock Enable |
| MCKOUTINV | Master Clock Output Invert |
| MCKDIV | Master Clock Division Factor |
| MCKOUTDIV | Master Clock Output Division Factor |